MAX1195ECM+TD【PDF 3/22 页】IC ADC 8BIT 40MSPS DL 48-TQFP

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Detailed Description

The MAX1195 uses a seven-stage, fully differential,

pipelined architecture (Figure 1) that allows for high-

speed conversion while minimizing power consump-

tion. Samples taken at the inputs move progressively

through the pipeline stages every half-clock cycle.

Including the delay through the output latch, the total

clock-cycle latency is five clock cycles.

Flash ADCs convert the held input voltages into a digi-

tal code. Internal MDACs convert the digitized results

back into analog voltages, which are then subtracted

from the original held input signals. The resulting error

signals are then multiplied by two, and the residues are

passed along to the next pipeline stages where the

process is repeated until the signals have been

processed by all seven stages.

Input Track-and-Hold Circuits

Figure 2 displays a simplified functional diagram of the

input T/H circuits in both track and hold mode. In track

mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b

are closed. The fully differential circuits sample the

input signals onto the two capacitors (C2a and C2b)

through switches S4a and S4b. S2a and S2b set the

common mode for the amplifier input, and open simul-

MAX1195

Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________

Pin Description (continued)

PIN

NAME

FUNCTION

D5A

Three-State Digital Output, Bit 5, Channel A

D6A

Three-State Digital Output, Bit 6, Channel A

D7A

Three-State Digital Output, Bit 7 (MSB), Channel A

REFOUT

Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor

divider.

REFIN

Reference Input. VREFIN = 2 x (VREFP – VREFN).

Bypass to GND with a > 0.1F capacitor.

REFP

Positive Reference I/O. Conversion range is

±(VREFP – VREFN).

Bypass to GND with a > 0.1F capacitor.

REFN

Negative Reference I/O. Conversion range is

±(VREFP – VREFN).

Bypass to GND with a > 0.1F capacitor.

VINA

STAGE 1

STAGE 2

D7A–D0A

VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED)

VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)

DIGITAL ALIGNMENT LOGIC

STAGE 6

STAGE 7

2-BIT FLASH

ADC

T/H

VINB

STAGE 1

STAGE 2

D7B–D0B

DIGITAL ALIGNMENT LOGIC

STAGE 6

STAGE 7

2-BIT FLASH

ADC

T/H

Figure 1. Pipelined Architecture—Stage Blocks

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